In integrated circuits that comprise output stages destined to drive discrete power devices or themselves integrated on the same chip containing the control circuitry, it is common to use a bootstrap capacitor to ensure correct powering of the driving stage. In these systems, it is essential that the bootstrap capacitance is charged in very short periods of time and this is usually attained through a diode emulator LDMOS transistor used to rapidly charge the bootstrap capacitance.
In the case of a driving circuit for a so-called High Side Driver (HSD) of a half-bridge output stage, the LDMOS transistor should be capable of charging the bootstrap capacitance when the HSD is referenced to low voltage (that is when its output is low). In addition, the LDMOS transistor should emulate a high impedance when the HSD is referenced to a high voltage (that is, when its output is high). These functioning conditions must be also ensured during the HSD switching phase from high to low voltage or vice versa. These conditions should also be ensured despite of the possible current injections resulting from the charging and discharging processes of the capacitances associated with the LDMOS integrated structure that must sustain the high voltage supply of the power device.
The publication WO 94/27370 discloses a half-bridge circuit comprising a driving module of the lower device and a driving floating module of the higher power device. The driving module of the higher transistor is realized in an isolated well region and a properly controlled LDMOS transistor emulates a high voltage charging diode for a bootstrap capacitor. In such a case it is necessary to control the effects of the parasitic bipolar junction transistors associated with the LDMOS integrated structure.
The European patent application EP-A-0743752, points out and describes certain conditions that cause problems related to the switch-on of parasitic transistors of the LDMOS integrated structure. The document also describes different circuit layouts capable of avoiding current consumption caused by the switch-on of parasitic transistors of the LDMOS integrated structure and avoiding the occurrence of conditions that may cause the destruction of the integrated device itself. FIG. 1 highlights the protecting circuit device described in the European patent application.
According to the approach described in the European patent application, there exists a functioning phase of the integrated circuit, referred to as UVLO, when the voltage supply Vs is less than the minimum switch-on voltage of the entire integrated device including also the LDMOS. During this phase, since SW1 and SW2 are both open, the potential of the VB body node of the LDMOS structure is kept at the circuit ground potential.
FIG. 1 shows that the LDMOS transistor is controlled through a bootstrap capacitor Cp charged by a diode D1 connected to the circuit supply node Vs by an inverter I01 driven by a Logic Control circuit as a function of a Low Gate Drive Signal and a second logic drive signal (UVLOb). The second logic drive signal is active during a phase in which the supply voltage Vs is lower than the minimum switch-on voltage of the integrated device.
Normally the LDMOS is commanded ON (node A brought to Vs by the inverter I01) only when the voltage on the LDMOS drain is lower than the source voltage. In contrast, if the LDMOS is accidentally switched on with VDS&gt;0, an undesired inverse current is generated from the drain of the LDMOS integrated transistor toward the supply node Vs. This inverse current may damage the device or in any case discharge the bootstrap capacitor.